Semiconductor device, semiconductor circuit and method for producing semiconductor device

ABSTRACT

The present invention is provided with a transmission line element having a ground wiring and a power supply wiring formed interposing an insulating film, on the power supply wiring on a semiconductor chip, lead or printed-circuit board, such that the capacitance per unit length of the transmission line element is boosted to set the characteristic impedance of the transmission line element for the high frequency range to an optimum value. In this way, the power supply wiring inclusive of the transmission line element can have a satisfactory decoupling performance.

TECHNICAL FIELD

The present invention relates to a semiconductor device and asemiconductor circuit, particularly to a semiconductor device and asemiconductor circuit provided with a decoupling circuit for reducing ahigh frequency noise that leaks through a power supply wiring.

BACKGROUND ART

In a digital circuit, high frequency noises generated incidentally toswitching operations of a semiconductor element cause electromagneticinterferences. This high frequency noise mainly includes high-orderharmonics of the fundamental clock frequency. For example, a part of thehigh frequency noises generated in an element in an LSI (Large ScaleIntegration) that makes a switching operation (hereinafter referred toas a switching element) propagates through the power supply wiring inthe LSI and further leaks through the package of interest into the powersupply wirings etc. of the printed-circuit board having the LSI mountedon.

The high frequency noises, which propagate through the power supplywirings, couple with the package and signal wirings on theprinted-circuit board, etc. in the LSI through electromagnetic inductionin the propagation paths. This electromagnetic coupling causes the highfrequency noises to superimpose on the signals carried through signalwirings to yield distortions of the signal voltages. Furthermore, in thecase where the surge impedance of the power supply wiring viewed fromthe switching element is high, the creation of the high frequency noisebrings about the creation of an electromagnetic wave, which is emittedfrom the signal cable and devices.

It is advantageous to arrange decoupling circuits adaptive to thefrequencies of the generated high frequency noises in most effectivepositions in order to relieve the above problems.

In the conventional decoupling circuit as described, for example, in JPH10-270643, a capacitor equivalent to a lumped constant has beenarranged between a power supply wiring and a ground potential wiring,because the sizes of the elements that constitute the circuit, such as atransistor, a resistor, a capacitor, etc., are small as compared withthe signal wavelength corresponding to the operation frequency of thesubject circuit.

Concerning other conventional decoupling circuits, JP 2001-168223describes a technology of increasing the decoupling capacitance betweenground and power supply rings; and JP H06-216309 describes a technologyof providing a decoupling capacitor on a lead frame of the semiconductordevice. For reference, the above technologies relate to decouplingcapacitors inserted between a power supply wiring and a ground potentialwiring provided on the same plane and fundamentally differ in theconstruction from the decoupling circuits of the present inventiondescribed later in that a power supply wiring and a ground potentialwiring are formed in different layers.

In the circuitry in which a capacitor is employed as a decouplingcircuit, it is necessary to take into account the inductance componentincluded in series with the connection terminal for the noises in a highfrequency range. In other words, a capacitor includes both capacitanceand inductance components representing a capacitive characteristic atthe frequency lower than the series resonance frequency of thecapacitance and inductance and an inductive characteristic at thefrequency higher than the series resonance frequency. Accordingly, whenusing a capacitor as a decoupling circuit, the decoupling circuitbecomes more inductive as the frequency becomes higher, resulting indegradation of the decoupling performance.

As a countermeasure to address such an issue, there is a method in whichmany capacitors are arranged in a distributed configuration near thepackage, or in the printed-circuit board in the LSI. Even if this methodis employed, however, the inductance of the terminals and transmissionlines for connecting the capacitors and power supply wiring has anunnegligible magnitude. For this reason, it has been difficult tooperate the capacitors as a decoupling circuit for a frequency range ofseveral hundreds MHz or higher.

The operations of recent digital circuits have been sped up to have theoperation frequencies as high as several GHz. Consequently, it isimperative that a decoupling circuit has an impedance kept at a lowvalue in the frequency range higher than hundreds MHz, or preferablyseveral tens GHz, in order to suppress an electromagnetic interferenceand improve a signal quality. For this end, it is necessary to develop acircuit element or an element structure differing from the conventionalcapacitor in order to be capable of retaining low impedance in a highfrequency range.

It is an object of the present invention to provide a semiconductordevice and a semiconductor circuit provided with a decoupling circuitcapable of retaining a low impedance up to the frequency higher thanseveral hundreds MHz, and preferably several tens GHz.

DISCLOSURE OF INVENTION

In order to achieve the above-described object, the present inventionimplements a transmission line element having a ground wiring and apower supply wiring formed interposing an insulating film, on the powersupply wiring on a semiconductor chip, lead or printed-circuit board,such that the capacitance per unit length of the transmission lineelement is increased to set the characteristic impedance of thetransmission line element to an optimum value for the high frequencyrange. In this way, the power supply wiring inclusive of thetransmission line element can have a satisfactory decouplingperformance. Because this construction of the transmission line providesa decoupling circuit having an excellent decoupling performance for ahigher frequency range than the conventional transmission line, thecreation of the high frequency noise that propagates from a switchingelement to a DC power supply through a power supply wiring is suppressedto result in suppression of the electromagnetic interference and alsoreduction of the distortion in the waveform of a signal attributed tothe high frequency noise generated by the switching element.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a circuit diagram representing a structure of the best mode ofthe semiconductor device according to the present invention;

FIG. 2 is a circuit diagram representing an equivalent circuit of thetransmission line element shown in FIG. 1;

FIG. 3 is a circuit diagram obtained by substituting a paralleladmittance for the equivalent circuit of the transmission line elementshown in FIG. 2;

FIG. 4 is a graph representing the relation between the characteristicimpedance of the transmission line element and the value of an elementS21 of the scattering matrix [S];

FIG. 5 is a cross-sectional view illustrating the typical structure ofthe wiring formed in a semiconductor device;

FIG. 6 is a cross-sectional side view illustrating a structure of thefirst embodiment of the semiconductor device according to the presentinvention;

FIG. 7 is a flow chart representing the method of fabricating thesemiconductor device of the first embodiment;

FIG. 8 is a cross-sectional side view illustrating the structure of thesecond embodiment of the semiconductor device according to the presentinvention;

FIG. 9 is a flow chart representing the first fabricating method forfabricating the semiconductor device of the second embodiment;

FIG. 10 is a flow chart illustrating the second method of fabricatingthe semiconductor device of the second embodiment;

FIG. 11 is a perspective view of the polysilicon and insulating filmillustrating the structure of a third embodiment of the semiconductordevice of the present invention;

FIG. 12 is a perspective view of the wiring illustrating the structureof a third embodiment of the semiconductor device of the presentinvention;

FIG. 13 is a cross-sectional view taken along an X-X′ line of thesemiconductor device shown in FIG. 11;

FIG. 14 is a cross-sectional view taken along a Y-Y′ line of thesemiconductor device shown in FIG. 11;

FIG. 15 is a flow chart illustrating the method of fabricating thesemiconductor device of the third embodiment;

FIG. 16 is a perspective view of the polysilicon and insulating filmrepresenting the structure of the semiconductor device of the fourthembodiment according to the present invention;

FIG. 17 is a perspective view of the wiring representing the structureof the semiconductor device of the fourth embodiment according to thepresent invention;

FIG. 18 is a cross-sectional view along an X-X′ line of thesemiconductor device shown in FIG. 16;

FIG. 19 is a cross-sectional view along a Y-Y′ line of the semiconductordevice shown in FIG. 16;

FIG. 20 is a flow chart illustrating the method of fabricating thesemiconductor device of the fourth embodiment;

FIG. 21 is a plan view illustrating an example of the structure of apackage of the semiconductor device;

FIG. 22 is an enlarged view illustrating the principal structure of thefifth embodiment of the semiconductor device according to the presentinvention;

FIG. 23 is a cross-sectional view along a Y-Y′ line of the semiconductordevice illustrated in FIG. 22;

FIG. 24 is a flow chart illustrating the method of fabricating thesemiconductor device of the fifth embodiment;

FIG. 25 is an enlarged view illustrating the principal structure of thesemiconductor device of the sixth embodiment according to the presentinvention;

FIG. 26 is a cross-sectional view along a Y-Y′ line of the semiconductordevice shown in FIG. 25;

FIG. 27 is a flow chart illustrating the method of fabricating thesemiconductor device of the sixth embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

Explanation is next presented regarding the present invention withreference to drawings.

FIG. 1 is a circuit diagram illustrating the most desirableconfiguration of the semiconductor device according to the presentinvention and FIG. 2 is a circuit diagram representing an equivalentcircuit of the transmission line element shown in FIG. 1.

As is shown in FIG. 1, the semiconductor device of the present inventionhas a structure such that a transmission line element 17 having acapacitive characteristic is inserted between a power supply wiring forsupplying a power supply current from a DC power supply 18 to switchingelement (for example, CMOS (Complementary Metal Oxide Semiconductor)inverter) 19 and the ground potential wiring. Transmission line element17 is arranged in the nearest possible position to switching element 19to allow a high frequency current created in switching element 19 toflow in the close vicinity of switching element 19. For reference, whileFIG. 1 represents the power supply wiring and the ground potentialwiring directly connected through transmission line element 17, actualtransmission line element 17 flows only a high frequency current betweenthe power supply and ground potential wirings through a capacitor butflows neither a DC current nor a signal current of a relatively lowfrequency.

As represented in FIG. 2, characteristic impedance Zc of transmissionline element 17 is represented in terms of impedance component Zzinserted in series between DC power supply 18 and switching element 19and impedance component Zy inserted in parallel with DC power supply 18.In addition, surge impedance Zs of switching element 19 is presumed asunknown. Further, characteristic impedance Zo of the power supply wiringdepends on inductance L connected in series between DC power supply 18and switching element 19 and the value of Zo is estimated to be severaltens to several hundreds Ω in the frequency region intended fordecoupling.

FIG. 3 is a circuit diagram in which the equivalent circuit of thetransmission line element shown in FIG. 2 is substituted with paralleladmittance Yc. For reference, FIG. 3 is a figure of the circuitrysimplified by neglecting impedance Zz connected in series between DCpower supply 18 and switching element 19 shown in FIG. 2.

The transmission characteristic of the circuit shown in FIG. 3 isrepresented by scattering matrix [S] shown in mathematical expression(1) below, $\begin{matrix}{\lbrack S\rbrack = {{\frac{1}{Y_{c}^{\prime} + 2}\begin{bmatrix}{- Y_{c}^{\prime}} & 2 \\2 & {- Y_{c}^{\prime}}\end{bmatrix}} = \begin{bmatrix}S_{11} & S_{12} \\S_{21} & S_{22}\end{bmatrix}}} & (1)\end{matrix}$where Yc′=Yc/Yo, Yo=1/Zo and Yc=1/Zc.

The reflection coefficient r and the transmission coefficient T of thecircuit viewed from the signal input terminal in FIG. 3 (on theobserver's left side of the figure=on the side of the switching element)can be represented by elements S11 and S21 of the above scatteringmatrix [S]. $\begin{matrix}{\Gamma = {S_{11} = {\frac{- Y_{c}^{\prime}}{Y_{c}^{\prime} + 2} = \frac{- 1}{{2( {Z_{c}/{Zo}} )} + 1}}}} & (2) \\{T = {S_{21} = {\frac{2}{Y_{c}^{\prime} + 2} = \frac{2( {Z_{c}/{Zo}} )}{{2( {Z_{c}/{Zo}} )} + 1}}}} & (3)\end{matrix}$where, if (impedance Zo of the power supply wiring)>>(impedance Zc oftransmission line element), then reflection coefficient Γ=−1,transmission coefficient T=0, and thus the high frequency currentgenerated in switching element 19 will not propagate through the powersupply wiring to flow into DC power supply 18.

The present invention forms a transmission line element on thesemiconductor chip, in the lead, or in the power supply wiring on theprint-circuit board and thereby provides the decoupling performance tothe power supply wiring including the transmission line by setting thecharacteristic impedance of the transmission line element to an optimumvalue for the high frequency range through increasing the capacitanceper unit length.

The transmission line element is formed through an arrangement suchthat, for example, a substrate (an electric conductor of polysilicon,metal, etc.) to which the ground potential is to be applied and thewiring through which the power supply current flows are arranged ondiffering layers across an insulating film. For increasing thecapacitance per unit length of the above transmission line element, thefollowing approaches can be intended:

-   -   1. The insulating film provided between the wiring and the        ground potential is thinned.    -   2. A material of a high dielectric constant is employed as an        insulating film.    -   3. A surface area is enlarged by forming a wiring in a        serpentine-curved shape, or creating corrugations on a surface        of the wiring. These three approaches can be applied in        combination.

The effective transmission line length of transmission line element 17,is set to be longer than one fourth of the wavelength ((λ/4)/ε^(1/2))that corresponds to the lowest frequency (hereinafter referred to as thelowest decoupling frequency) in the frequency range intended for thedecoupling. As a result of this setting, the characteristic impedance oftransmission line element 17 is represented as (L/C)^(1/2) independentof a frequency in the frequency range intended for decoupling, wherein λstands for the wavelength corresponding the minimum frequency, ε for aspecific dielectric constant of the insulating film, L for an inductanceper unit length of transmission line element 17 and C for a capacitanceper unit length of transmission line element 17.

In addition, it is necessary in order to enable the decouplingperformance over a wide frequency range to lengthen the effective lengthof transmission line element 17. It is desirable, however, to restrainan increase in a layout area of the transmission line to the minimumfrom the view of realization of downsizing and highly densifying asemiconductor device. For this reason, in the present invention,transmission line element 17 is formed in a serpentine-curved pattern,or to have corrugations on the surface while keeping the distancebetween the ground and power supply wirings constant, thereby enablingincrease in the wiring width and length without increasing the layoutarea of the transmission line.

In addition, the present invention implements the transmission lineelement on a semiconductor chip, wherein the transmission line elementis configured to have a capacitive characteristic for the highestfrequency of the high frequencies generated by the switching element onthe semiconductor chip.

Further, the present invention implements the transmission line elementon the lead of a semiconductor device, wherein the transmission lineelement has a capacitive characteristic for a substantially lowfrequency range than the case with the transmission line elementimplemented on a semiconductor chip.

Alternatively, the present invention implements the transmission lineelement on a print-circuit board, wherein the transmission line elementhas a capacitive characteristic for a substantially low frequency rangethan the case with the transmission line element implemented on a leadof a semiconductor device.

The semiconductor circuit according to the present invention is mountedwith a plurality of transmission line elements having differenteffective frequency zones arranged in a plurality of locations such aslocations of a chip and a lead of a semiconductor device or aprinted-circuit board in a distributed configuration in order to widenthe frequency range intended for the decoupling performance and also torealize high-density deployments in a semiconductor device. In thiscase, it is desirable to set the characteristic impedance of eachtransmission line element such that a voltage variation of DC powersupply is 5% or less.

Furthermore, it is necessary to configure the insulating film to have adielectric loss to some extent in order to prevent the incident wave onthe transmission line element from externally leaking. This dielectricloss in the insulating film is preferably as large as the heatconsumption of the electromagnetic wave incident on the transmissionline element

The present invention offers a decoupling circuit having good decouplingperformance up to the frequency range higher than the conventional caseby adopting the transmission line element having the above-describedstructure as a decoupling circuit. As a result, the high frequencynoises, which transmit from the switching element to the DC power supplyvia the power supply wiring, are restrained, whereby the electromagneticinterference is reduced and also the distortion in a signal waveformcaused by the high frequency noises produced in the switching element isreduced.

Embodiment

Explanation is next presented regarding an embodiment of the presentinvention with reference to the drawings.

Explanation first regards the relation between the characteristicimpedance of the transmission line element and an element S21 of thescattering matrix [S] (transmission coefficient T).

FIG. 4 is a graph representing the relation between the characteristicimpedance of the transmission line element and an element S21 of thescattering matrix [S]. For reference, FIG. 4 represents the examples inwhich the characteristic impedances Zo equal 50 Ω and 100 Ω,respectively.

While the value of a characteristic impedance of a power supply wiringZ0 generally depends on whether the wiring is formed on aprinted-circuit board or it is formed on a chip of a semiconductordevice, the characteristic impedance can be set to the level ofapproximately 50 Ω to 200 Ω. Further, current digital circuits requirethe value of S21 to be no more than −40 dB for the decouplingperformance.

As shown in FIG. 4, in the case where the characteristic impedance ofthe power supply wiring Zo=50 Ω, which is a severe condition, it isnecessary to make the characteristic impedance of the transmission lineelement Zc no more than 0.3 Ω in order to have S21 no more than −40 dB.

FIG. 5 is a cross-sectional view typically illustrating the structure ofthe wiring formed in a semiconductor device.

As shown in FIG. 5, the transmission line formed in a semiconductordevice is configured such that insulating film (oxide film) 21 is formedon ground substrate 20 and wiring 22 is formed on insulating film 21.Wiring 22 is formed using, for example, aluminum and is 1 mm in wiringlength and approximately 50 μm in width. In addition, insulating film 21is formed about 5000 Å in film thickness using, for example, SiO₂ havinga specific dielectric constant of about 4. Ground substrate 20 is formedof, for example, polysilicon doped with impurities at a highconcentration and having a resultant reduced resistance. Characteristicimpedance Zc of the transmission line formed of the above-describedground substrate 20, insulating film 21 and wiring 22 is about 50 Ω.

Accordingly, in order to make the characteristic impedance Zc of thetransmission line element 0.3 Ω or smaller, it is necessary to reducethe characteristic impedance to about 1/170 and increase the capacitanceper unit length to 30,000 times for the example of the structure shownin FIG. 5.

Explanation below regards embodiments of the present invention.

First Embodiment

Explanation is first given regarding a first embodiment of thesemiconductor device according to the present invention.

FIG. 6 is a cross-sectional side view illustrating a structure of thefirst embodiment of the semiconductor device according to the presentinvention.

As represented in FIG. 6, the semiconductor device of the firstembodiment has a structure in which there are provided silicon substrate1, silicon oxide film 2 formed on silicon substrate 1, polysilicon 3doped with high concentration impurities formed on silicon oxide film 2,insulating film 4 of a high specific dielectric constant formed of, forexample, LaAlO₃ film provided on polysilicon 3 and wiring 5 formed of,for example, aluminum provided on insulating film 4.

For reference, the direction of transmission of a signal carried bywiring 5 in FIG. 6 is taken in the direction perpendicular to thesurface of the page.

The transmission line element of the first embodiment has insulatingfilm 4 formed of about 10 Å thick LaAlO₃ film having a specificdielectric constant of about 24 with polysilicon 3, insulating film 4and wiring 5 formed in a corrugated pattern, whereby the width of thewiring is increased to about 10 times and also the capacitance per unitlength is increased to about 30,000 times as compared with the generalexample of structure shown in FIG. 5 without changing the layout area ofthe transmission line. For reference, the thickness of insulating film 4is kept constant by keeping the distance between polysilicon 3 andwiring 5 constant.

Explanation is next presented regarding the method of fabricating thesemiconductor device of the first embodiment.

FIG. 7 is a flow chart representing the method of fabricating thesemiconductor device of the first embodiment.

As is represented in FIG. 7, in the first embodiment, silicon oxide film2 is first formed on silicon substrate 1 (Step S1), polysilicon 3 isformed on silicon oxide film 2, and polysilicon 3 is processed to reduceresistance to the level of metal by implantation of impurities such asphosphorus (Step S2).

Next, patterning process is carried out on polysilicon 3 through thewell-known photolithography to form corrugations (Step S3).Subsequently, insulating film 4 made of LaAlO₃ film is formed in about10 Å thickness on polysilicon 3 (Step S4) and finally wiring 5 made ofaluminum is formed on insulating film 4 (Step S5).

Second Embodiment

FIG. 8 is a cross-sectional side view illustrating the structure of thesecond embodiment of the semiconductor device according to the presentinvention.

As represented in FIG. 8, the semiconductor device of the secondembodiment has a structure in which there are provided silicon substrate1, silicon oxide film 2 formed on silicon substrate 1, polysilicon 3doped with high concentration impurities, insulating film 4 of a highspecific dielectric constant formed of, for example, LaAlO₃ filmprovided on polysilicon 3 and wiring 5 formed of, for example, aluminumprovided on insulating film 4, just like the semiconductor device of thefirst embodiment.

The transmission line element of the second embodiment has insulatingfilm 4 formed of about 10 Å thick SrTiO₃ film having a specificdielectric constant of about 16 with the contact surfaces of thepolysilicon 3 and insulating film 4 and the contact surfaces of theinsulating film 4 and wiring 5 formed in a corrugated pattern, thecontact surfaces being modified by finer ridges and depressions, wherebythe width of the wiring is increased to about 10 times and also thecapacitance per unit length is increased to about 40,000 times ascompared with the general example of structure shown in FIG. 5 withoutchanging the layout area of the transmission line.

Explanation next regards the method of fabricating the semiconductordevice of the second embodiment.

Two fabrication methods are considered for fabricating the semiconductordevice of the second embodiment. A first fabrication method is firstexplained with reference to FIG. 9.

FIG. 9 is a flow chart representing the first fabrication method forfabricating the semiconductor device of the second embodiment.

As shown in FIG. 9, in the first fabrication method, silicon oxide film2 is first formed on silicon substrate 1 (Step S11), on whichpolysilicon 3 is formed, and the polysilicon 3 is processed to reducethe resistance to the level of metal by implanting phosphor ions etc(Step S12).

Next, patterning process is carried out on polysilicon 3 through thewell-known photolithography technology to form corrugations(Step S13).Subsequently, further depressions are formed on the surface ofpolysilicon 3 through the method such as spraying wet etching solution(Step S14).

Next, insulating film 4 of SrTiO₃ is formed on polysilicon 3 (Step S15)and finally wiring 5 of aluminum is formed on insulating film 4 (StepS16).

Explanation is next presented regarding the second method of fabricatingthe semiconductor device of the second embodiment with reference to FIG.10.

FIG. 10 is a flow chart illustrating the second method of fabricatingthe semiconductor device of the second embodiment.

As is represented in FIG. 10, in the second fabricating method, siliconoxide film 2 is first formed on silicon substrate 1 (Step S21),polysilicon 3 is formed on silicon oxide film 2, and implantation ofphosphor ions etc is implemented on the polysilicon 3 to reduce theresistance of polysilicon 3 to the level of metal (Step S22).

Next, a patterning process is carried out on polysilicon 3 through thewell-known photolithography technology to create corrugations (StepS23). Subsequently, silicon is locally grown on polysilicon 3 in avapor-phase growth furnace while introducing silane (SiH4) to produceprotrusions (Step S24).

Next, insulating film 4 made of SrTiO₃ film is formed on polysilicon 3(Step S25), and finally wiring 5 of aluminum is formed on insulatingfilm 4 (Step S26).

For reference, if the lowest decouplable frequency is set to 10 GHz(wavelength λ=30 mm) for the above-described transmission line elementmade up of polysilicon 3, insulating film 4 and wiring 5, then thetransmission line length is (λ/4)/ε^(1/2) or greater. The length oftransmission line element is 1.5 mm or greater in the first embodiment,because LaAlO₃ having the specific dielectric constant of about 24 isemployed for insulating film 4. Further, the length of transmission lineelement is 1.88 mm or greater in the second embodiment, because SrTiO₃having the specific dielectric constant of about 16 is employed forinsulating film 4.

Third Embodiment

FIG. 11 is a perspective view of the polysilicon and insulating filmillustrating a third embodiment of the semiconductor device of thepresent invention. FIG. 12 is a perspective view of the wiringillustrating a third embodiment of the semiconductor device of thepresent invention. FIG. 13 is a cross-sectional view taken along an X-X′line of the semiconductor device shown in FIG. 11. FIG. 14 is across-sectional view taken along a Y-Y′ line of the semiconductor deviceshown in FIG. 11. For reference, FIG. 11 through FIG. 14 are thedrawings in which silicon substrate 1 and silicon oxide film 2 areomitted from the constituent elements that make up the transmission lineelement.

As shown in FIG. 11 through FIG. 14, the transmission line element ofthe third embodiment has a structure in which polysilicon 3, insulatingfilm 4 and wiring 5 are formed in a corrugated pattern in the direction(X-X′) perpendicular to the signal transmission direction and alsoformed in a corrugated pattern in the signal transmission direction(Y-Y′). As a result of this structure, the wiring width and length areincreased entailing an increase in a capacitance per unit length of thetransmission line element without necessitating any increase in thelayout area of the transmission line element, thereby widening the rangeof an effective decouplable frequency of the transmission line length.

Explanation is next given regarding a method of fabricating thesemiconductor device of the third embodiment with reference to FIG. 15.

FIG. 15 is a flow chart illustrating the method of fabricating thesemiconductor device of the third embodiment.

As is represented in FIG. 15, in the third embodiment, silicon oxidefilm 2 is first formed on silicon substrate 1 (Step S31), polysilicon 3is formed on silicon oxide film 2, and implantation of phosphor ionsetc. is implemented on the polysilicon 3 to reduce the resistance ofpolysilicon 3 to the level of metal (Step S32).

Next, a patterning process is carried out on polysilicon 3 through thewell-known photolithography technology to create corrugations arrangedin both of the signal transmission direction and the directionperpendicular to the signal transmission direction (Step S33).

Next, insulating film 4 made of an LaAlO₃ film is formed about 10 Å inthickness on polysilicon 3 (Step S34) and finally wiring 5 of aluminumis formed on insulating film 4 (Step S34), wherein the forms ofinsulating film 4 and wiring 5 are corrugated in each of the signaltransmission direction and the direction perpendicular to the signaltransmission direction, as is the case of polysilicon 3.

It is possible in the present embodiment to increase the wiring widthand wiring length to about 10 times those in the first and secondembodiments without increasing the layout area of the transmission line.As a result, even if the lowest effective decouplable frequency is setto 1 GHz, i.e., 1/10 that of the first and second embodiments, a lengthof about 1.5 mm suffices for the length of the transmission line of thetransmission line element.

Fourth Embodiment

FIG. 16 through FIG. 19 are diagrams illustrating the structure of thesemiconductor device of the fourth embodiment according to the presentinvention. FIG. 16 is a perspective view of the polysilicon andinsulating film representing the structure of the semiconductor deviceof the fourth embodiment according to the present invention. FIG. 17 isa perspective view of the wiring representing the structure of thesemiconductor device of the fourth embodiment according to the presentinvention. FIG. 18 is a cross-sectional view along an X-X′ line of thesemiconductor device shown in FIG. 16, and FIG. 19 is a cross-sectionalview along a Y-Y′ line of the semiconductor device shown in FIG. 16. Forreference, FIG. 16 through FIG. 19 are the drawings in which siliconsubstrate 1 and silicon oxide film 2 are omitted from the constituentelements that make up the transmission line element.

As shown in FIG. 16 through FIG. 19, the transmission line element ofthe fourth embodiment has a structure in which polysilicon 3, insulatingfilm 4 and wiring 5 are formed so as to have corrugations arranged inthe direction (X-X′) perpendicular to the signal transmission directionwith each corrugation being worked to have a plurality of ridges in theside surface. As a result of this structure, the wiring width isincreased entailing an increase in a capacitance per unit length of thetransmission line without necessitating any increase in the layout areaof the transmission line, thereby widening the range of an effectivedecouplable frequency of the transmission line element, just like thethird embodiment.

Explanation is next given regarding the method of fabricating thesemiconductor device of the fourth embodiment with reference to FIG. 20.

FIG. 20 is a flow chart illustrating the method of fabricating thesemiconductor device of the fourth embodiment.

As is represented in FIG. 20, in the fourth embodiment, silicon oxidefilm 2 is first formed on silicon substrate 1 (Step S41), polysilicon 3is formed on silicon oxide film 2, and implantation of phosphor ionsetc. is implemented on the polysilicon 3 to reduce the resistancethereof to the level of metal (Step S42).

Next, a patterning process is carried out on polysilicon 3 through thewell-known photolithography technology, corrugations arranged in thedirection perpendicular to the signal transmission direction arecreated, and each corrugation is worked to have a plurality of ridges(Step S43).

Next, insulating film 4 made of an LaAlO₃ film is formed about 10 Åthick on polysilicon 3 (Step S44) and finally wiring 5 of aluminum isformed on insulating film 4 (Step S45), wherein the forms of insulatingfilm 4 and wiring 5 are corrugated in the direction perpendicular to thesignal transmission direction and their side surface have a plurality ofridges, just like polysilicon 3.

It is possible in the present embodiment as well to increase the wiringwidth to about 10 times that of the first and second embodiments withoutincreasing the layout area of the transmission line. As a result, evenif the lowest effective decouplable frequency is set to 1 GHz, i.e.,1/10 that of the first and second embodiments, a length of about 1.5 mmsuffices for the length of the transmission line of the transmissionline element.

For reference, the transmission line elements illustrated in the firstthough fourth embodiments allow an increase in the wiring width orwiring length without increasing the layout area of the transmissionline as well if it is configured so as to set the direction oftransmitting a signal in the direction different by 90 degrees (i.e., ina horizontal direction with respect to the page, or in the X-X′direction). Thus, it is possible to obtain the same advantage asdescribed above.

Further, if the transmission line element is made longer in order toattain decoupling performance for a lower frequency and consequentlybecomes unable to be mounted on the semiconductor chip, then it ispossible to implement the transmission line element, described inconnection to the above-described first through fourth embodiments, on aprinted-circuit board or a lead of a package. In this regard, however,it is preferred to arrange the transmission line element near theswitching element to result in less degradation in the decouplingperformance.

Thus, it is preferred to implement the transmission line elements in aplurality of locations on a chip and a lead of a semiconductor device,or a printed-circuit board etc. depending on the size in order to widenthe frequency zone intended for decoupling and also to realizehigh-density integration of a semiconductor device.

Fifth Embodiment

The semiconductor device of the fifth embodiment is configured such thatthe transmission line element exemplified in each of the above-describedfirst through fourth embodiments is implemented on a lead of asemiconductor device.

Explanation first regards a general structure of a package of asemiconductor device.

FIG. 21 is a plan view illustrating an example of the structure of apackage of the semiconductor device.

As illustrated in FIG. 21, the semiconductor device has a structurehaving semiconductor chip 32, on which circuits are formed, fixed to diepad section 31 by means of mounting material. Internal pads (not shown)are formed on the surface of semiconductor chip 32, and the internalpads are connected respectively with a plurality of leads 33 arrangedaround the periphery of die pad 31 through the use of bonding wires. Diepad 31, semiconductor chip 32, bonding wires and parts of leads aresealed by resin mold layer 34.

In the present embodiment, the transmission line element described inany of the above-described first through fourth embodiments isimplemented on lead for a power supply wiring (hereinafter, referred toas a power supply lead) 33-1 of a plurality of leads 33 shown in FIG.21.

FIG. 22 is an enlarged view illustrating the pricipal structure of thefifth embodiment of the semiconductor device according to the presentinvention.

FIG. 22 is a view of power supply lead 7 and other leads of thesemiconductor device in an enlarged representation showing anarrangement of transmission line element 6 mounted on power supply lead7.

Transmission line element 6 has a construction made up of polysilicon 3,insulating film (for example, LaAlO₃) 4, and wiring 5 as illustrated inany of the first through fourth embodiments.

FIG. 23 is a cross-sectional view along a Y-Y′ line of the semiconductordevice illustrated in FIG. 22.

As shown in FIG. 23, the semiconductor device of the present embodimenthas a construction in which transmission line element 6 is formed onmetal ground (ground potential) surface 10 fixed to, for example, apackage of a semiconductor device and epoxy resin layers 9 are formed onground surface 10 so as to sandwich transmission line element 6 ofinterest.

Power supply lead 7 is formed on each of epoxy resin layers 9, andtransmission line element 6 and the end of power supply lead 7 on eachof epoxy resin layers 9 are connected through end line 6 a, 6 b.Transmission line element 6 of the present embodiment is formed thinnerthan epoxy resin layers 9. Consequently, transmission line element 6formed thinner than insulating film 4 yields a large capacitance oftransmission line element 6. For reference, FIG. 23 represents anarrangement in which lead 8 is omitted.

Explanation next regards the method of fabricating the semiconductordevice of the fifth embodiment.

FIG. 24 is a flow chart illustrating the method of fabricating thesemiconductor device of the fifth embodiment.

As represented in FIG. 24, the fifth embodiment forms first epoxy resinlayers 9 having a specific dielectric constant of 4 and about 1 mm inthickness on metal ground surface 10 (Step S51).

Next, metal leads 8 (not shown) and power supply lead 7 each 1 mm wideand about 20 mm long (the length of the upper layer section only) areformed on epoxy resin layers 9 (Step S52).

Subsequently, transmission line element 6, which is thinner than epoxyresin layers 9, is formed in the site sandwiched between epoxy resinlayers 9 according to the method described in any of the above-describedfirst through fourth embodiments (Step S53). The end portion oftransmission line element 6 is bonded to power supply leads 7 formed onepoxy resin layers 9 by solder etc. For reference, the polysilicon(ground potential wiring: not shown) of transmission line element 6 isconnected to metal ground surface 10.

In this construction, if, for example, the lowest decouplable frequencyof transmission line element 6 is set to 1 GHz, then the length oftransmission line element 6 is about 15 mm, provided that transmissionline element 6 is configured in accordance with the first embodiment,and the length is about 1.5 mm, provided that transmission line element6 is configured in accordance with the third embodiment. Further, if thelowest decouplable frequency is set to 100 MHz, then the length oftransmission line element 6 is about 150 mm, provided that transmissionline element 6 is configured in accordance with the first embodiment,and the length is about 15 mm, provided that transmission line element 6is configured in accordance with the third embodiment.

If it is assumed that the length of power supply lead 7 of thesemiconductor device is 20 mm and the length of transmission lineelement 6 that can be mounted on the lead of interest is 15 mm, thedecoupling effect can be expected in 1 GHz and higher through the use oftransmission line element 6 described in the first embodiment and in 100MHz and higher through the use of transmission line element 6 describedin the third embodiment.

It is to be noted that, while the above explanation has been given onthe presumption that metal ground surface 10 is fixed to the package ofthe semiconductor device, it is possible to connect the polysilicon ofthe transmission line element to the ground potential wiring on theprint-circuit board in the case where the package lacks a groundsurface.

Sixth Embodiment

The semiconductor device of the sixth embodiment has a construction inwhich any of the transmission line elements exemplified in the firstthrough fourth embodiments is implemented on a lead of the semiconductordevice.

FIG. 25 is an enlarged view illustrating the principal structure of thesemiconductor device of the sixth embodiment according to the presentinvention.

FIG. 25 is an enlarged view of power supply lead 7 and other leads 8 ofthe semiconductor device illustrating an arrangement of transmissionline element 6 mounted on power supply lead 7.

FIG. 26 is a cross-sectional view along a Y-Y′ line of the semiconductordevice shown in FIG. 25.

As represented in FIG. 26, the semiconductor device of the presentinvention is configured such that metal ground (ground potential)surface 10 is formed on ceramic substrate (insulator substrate) 12 fixedto, for example, a package of a semiconductor device and wiring 14 isformed on metal ground surface 10 through insulating film 13 of a highdielectric constant to yield transmission line element 41.

Ceramic layer (insulating film) 11 is formed on transmission lineelement 41, which is connected to power supply lead 7 formed on ceramiclayer 11 of interest through a through-hole provided in ceramic layer11.

Specifically, about 1 mm thick ceramic layer 11 made of alumina having aspecific dielectric constant of 8 is formed on metal ground surface 10and metal leads 8 (not shown) and two power supply leads 7 each 1 mmwide and about 20 mm long are formed on ceramic layer 11.

While in the first through fourth embodiments, the width of transmissionline element is set to 50 μm, it is set to about 1 mm to accord with thewidth of power supply lead 7 in the present embodiment.High-dielectric-constant insulating film 13 is formed about 10 Å inthickness through the use of, for example, an LaAlO₃ film having aspecific dielectric constant of 24.

For reference, in the present embodiment, while transmission lineelement 41 is not formed in a corrugated pattern, it satisfactorilyclears the presumed standard, because the width of the transmission lineis 20 times as compared to those of the first and second embodiments andconsequently the capacitance per unit length attains about 60,000 timesthat of the wiring in the general case shown in FIG. 5.

In the present embodiment, if the lowest decouplable frequency of thetransmission line element is prescribed to be, for example, 1 GHz, thenthe length of the transmission line element becomes 15 mm or longer.Wiring 14 of transmission line element 41 is connected to power supplyleads 7 in both ends of wiring 14, and ground surface 10 is used incommon for the ground-potential wiring of transmission line element 41.

Explanation next regards the method of fabricating the semiconductordevice of the sixth embodiment.

FIG. 27 is a flow chart illustrating the method of fabricating thesemiconductor device of the sixth embodiment.

As shown in FIG. 27, in the sixth embodiment, ground surface 10 formedof a metal layer is first formed on ceramic substrate 12 of alumina etc.(Step S61) and insulating film 13 about 10 Å thick formed of an LaAlO₃film is formed on ground surface 10 of interest (Step S62).

Next, wiring 14 about 1 mm wide made of tungsten etc. is formed oninsulating film 13 (Step S63). This piece is referred to as ceramic A.

Next, ceramic layer 11 having an opening (through-hole) formed thereinis provided separately from ceramic A, and power supply leads 7 about 1mm wide of tungsten etc. are formed to connect the top section ofceramic layer 11, the internal wall of the through-hole, and the bottomsection of the through-hole (Step S64). This piece is referred to asceramic B.

Finally, the above-described ceramic A and ceramic B are affixedtogether and sintered to combine integrally (Step S65). In this step,the parts of power supply leads 7 formed in the bottom portions of thethrough-hole provided in ceramic layer 11 are bonded to both ends ofwiring 14 formed on insulating film 13.

For reference, in the above-described first to sixth embodiments, whilecharacteristic impedance Zc of 0.3 Ω or less is preset for the designbasis of the transmission line element, the characteristic impedance Zcof an actual transmission line element depends on a required decouplingperformance, the construction, material of the leads and printed-circuitboard of the semiconductor device. Thus, it is preferred to set optimumvalues depending on such conditions.

In addition, regarding the transmission line elements illustrated asexamples in the above first through sixth embodiments, it is preferredto properly change the dielectric constant and thickness of theinsulating film, the width and length of transmission line, the densityof the corrugations, the aspect ratio of the corrugation, the shape ofthe corrugation, etc. according to the design basis.

Furthermore, regarding the foregoing first through sixth embodiments,while explanation of the methods of fabricating transmission lineelements is given on the presumption of a silicon process, the methodsare applicable to the fabrication process other than the silicon processsuch as gallium arsenide process.

Furthermore, the following materials can be used for the insulating filmof the transmission line element: epoxy resin having the same dielectricconstant of about 4 as the silicon oxide film; SiO, silicon nitride,TaO₃, TiO₂, Al₂O₃, and MgO having a specific dielectric constant ofabout 8; SrTiO₃ and ZrO₂ having a specific dielectric constant of about16; LaAlO₃ having a specific dielectric constant of about 24; BST(titanium oxide barium strontium) having a specific dielectric constantof about 300; and PZT (lead zirconate titanate) having a specificdielectric constant of about 1000, etc.

1. A semiconductor device comprising: a plurality of transmission lines,formed in a semiconductor chip, each formed of a ground wiring to havethe ground potential and a power supply wiring to carry a power supplycurrent with an insulating film interposed between the ground wiring andthe power supply wiring; and a transmission line element formed in asemiconductor chip and arranged to relay said power supply currentcarried between said transmission lines, said transmission line elementbeing formed of said ground wiring and said power supply wiring with aninsulating film interposed between the ground wiring and the powersupply wiring and having a characteristic impedance sufficiently low ascompared to the characteristic impedance of said transmission line. 2.The semiconductor device according to claim 1, wherein said transmissionline element has a large capacitance per unit length such that thecharacteristic impedance thereof is low enough as compared to thecharacteristic impedance of said transmission line.
 3. The semiconductordevice according to claim 1, wherein the effective length of saidtransmission line element is a transmission line length longer than onefourth of a wavelength corresponding to the lowest frequency in thefrequency range intended for decoupling.
 4. (canceled)
 5. Thesemiconductor device according to claim 1, wherein said transmissionline element has said ground wiring and said power supply wiring formedin a corrugated form with a separation thereof kept at a constantdistance.
 6. The semiconductor device according to claim 5, wherein saidtransmission line element has at least either depressions or protrusionson said ground wiring, said insulating film and said power supplywiring.
 7. The semiconductor device according to claim 5, wherein saidtransmission line element is formed in a corrugated form withcorrugations arranged in a direction perpendicular to said signaltransmission direction.
 8. The semiconductor device according to claim5, wherein said transmission line element is formed in a corrugated formwith corrugations arranged in said signal transmission direction.
 9. Thesemiconductor device according to claim 5, wherein said transmissionline element is formed in a corrugated form with corrugations arrangedboth in a signal transmission direction and in a direction perpendicularto said signal transmission direction.
 10. The semiconductor deviceaccording to claim 5, wherein the surfaces formed in a corrugated formof said ground wiring, said insulating film, and said power supplywiring of said transmission line element are each further formed in aform having a plurality of ridges
 11. (canceled)
 12. The semiconductordevice according to claim 1, further comprising: a plurality oftransmission lines implemented on power supply leads each for supplyinga power supply current from an external circuit, each formed of a groundwiring to have the ground potential and a power supply wiring to carry apower supply current with an insulating film interposed between theground wiring and the power supply wiring; and a transmission lineelement implemented on power supply leads and arranged to relay saidpower supply current carried between said transmission lines, saidtransmission line element being formed of said ground wiring and saidpower supply wiring with a second insulating film interposed between theground wiring and the power supply wiring, and further said transmissionline element having a characteristic impedance sufficiently low ascompared to the characteristic impedance of said transmission line. 13.The semiconductor device according to claim 12, further provided with aresin layer formed on a ground potential surface interposing saidtransmission line element, with the ends of said power supply leadsbeing connected to said transmission line element and said power supplyleads being formed on said resin layer, wherein said transmission lineelement is formed thinner than said resin layer.
 14. The semiconductordevice according to claim 12, further comprising: a transmission lineelement formed on a part of an insulating substrate of a package, and aninsulator layer mounted on said transmission line element and providedwith a through-hole that passes from the top to the bottom of theinsulator layer, wherein said power supply leads are formed on said topand connected to said power supply wiring of said transmission lineelement through said through-hole.
 15. A semiconductor circuit, providedwith: a semiconductor device according to claim 12, and aprinted-circuit board on which said semiconductor device is mounted,provided with a plurality of transmission lines each formed of a groundwiring to have the ground potential and a power supply wiring to carry apower supply current with an insulating film interposed between theground wiring and the power supply wiring, and a transmission lineelement arranged to relay said power supply current carried between saidtransmission lines, said transmission line element being formed of saidground wiring and said power supply wiring with a second insulating filminterposed between the ground wiring and the power supply wiring andhaving a characteristic impedance sufficiently low as compared to thecharacteristic impedance of said transmission line.
 16. Thesemiconductor circuit according to claim 15, wherein said transmissionline element has a characteristic impedance to yield a variation in adirect-current power supply voltage applied to said power supply wiringto be 5% or less.
 17. The semiconductor circuit according to claim 15,wherein the transmission line element mounted on a semiconductor chip ofsaid semiconductor device has capacitive characteristics for the highestfrequency of the high frequencies generated in said semiconductor chip,the transmission line element mounted on the power supply lead of saidsemiconductor device has capacitive characteristics for the frequencyrange lower than the frequency range for the transmission line elementmounted on a semiconductor chip, and the transmission line elementmounted on the printed-circuit board has capacitive characteristics forthe frequency range lower than the frequency range for the transmissionline element mounted on the power supply lead of said semiconductordevice.
 18. A method of fabricating a semiconductor device having aplurality of transmission lines each formed of a ground wiring to havethe ground potential and a power supply wiring to carry a power supplycurrent with an insulating film interposed between the ground wiring andthe power supply wiring, including an element-forming step of forming atransmission line element arranged to relay said power supply currentcarried between said transmission lines, said transmission line elementbeing formed in a semiconductor chip and formed of said ground wiringand said power supply wiring with a second insulating film interposedbetween the ground wiring and the power supply wiring, and saidtransmission line element having a characteristic impedance sufficientlylow as compared to the characteristic impedance of said transmissionline.
 19. The method of fabricating a semiconductor device according toclaim 18, wherein said element-forming step comprising the steps of:forming said ground wiring; patterning said ground wiring and formingthe ground wiring in a corrugated form; forming said insulating film onsaid ground wiring; and forming said power supply wiring on saidinsulating film.
 20. The method of fabricating a semiconductor deviceaccording to claim 18, wherein said element-forming step comprising thesteps of: forming said ground wiring; patterning said ground wiring andforming corrugations arranged in a signal transmission direction andalso in the direction perpendicular to said signal transmissiondirection on the ground wiring; forming said insulating film on saidground wiring; and forming said power supply wiring on said insulatingfilm.
 21. The method of fabricating a semiconductor device according toclaim 18, wherein said element-forming step comprising the steps of:forming said ground wiring; patterning said ground wiring and formingthe ground wiring in a corrugated form; further forming depressions onthe corrugated surface; forming said insulating film on said groundwiring; and forming said power supply wiring on said insulating film.22. The method of fabricating a semiconductor device according to claim18, wherein said element-forming step comprising the steps of: formingsaid ground wiring; patterning said ground wiring and forming the groundwiring in a corrugated form; further forming ridges on the corrugatedsurface; forming said insulating film on said ground wiring; and formingsaid power supply wiring on said insulating film.
 23. The method offabricating a semiconductor device according to claim 18, wherein saidelement-forming step comprising the steps of: forming said groundwiring; patterning said ground wiring and forming the ground wiring suchthat the ground wiring is formed in a corrugated form and further ridgesare formed on the corrugated surface; forming said insulating film onsaid ground wiring; and forming said power supply wiring on saidinsulating film.
 24. The method of fabricating a semiconductor deviceaccording to claim 18, further comprising steps of: forming resin layersdividedly on a part of a ground potential surface in a package of asemiconductor device; forming resin layers in a divided configuration onsaid ground potential surface; forming power supply leads for supplyinga power supply current from an external circuit on each of said resinlayers; and forming a transmission line element having a power supplywiring arranged on said ground potential surface interposing aninsulating film, in the position to relay said power supply leads on thedivided resin layers, wherein said transmission line element has acharacteristic impedance low enough compared to the characteristicimpedance of said transmission line.
 25. The method of fabricating asemiconductor device according to claim 18, further comprising steps of:forming a ground potential surface on a part of an insulating substratein a package of a semiconductor device; forming a ground potentialsurface on said insulating substrate; forming a transmission lineelement having a power supply wiring arranged on said ground potentialsurface interposing an insulating film; forming a through-hole in aninsulating layer provided in a piece separate from said insulatingsubstrate; forming power supply leads for supplying a power supplycurrent supplied to the top of said insulating layer and carried fromthe top of said insulating layer to the bottom of said through-holethrough the internal wall of said through-hole; and affixing saidinsulating layer to said insulating substrate, and connecting said powersupply leads in the bottom of the through-hole and the power supplywiring formed on said transmission line element, respectively.